This happens to be a negative edge triggered JK flip flop. I used boolean algebra and found D = E' and E = D'. Given the propagation delay I thought this was
JK Flip-flop: Positive Edge Triggered and Negative Edge-Triggered Flip-Flop
Edge-Triggered J-K Flip-Flop
For each of the positive edge-triggered JK flip-flop used
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digital logic - Confusion about when a JK flip flop is triggered - Electrical Engineering Stack Exchange
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Edge-Triggered J-K Flip-Flop
Solved For a negative-edge-triggered J-K flip-flop with | Chegg.com
Why does the JK flip-flop toggles on the 'negative edge' of its clock input when its inputs are connected to +v (i.e when j=1 , k=1)? - Quora
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JK Flip-Flop Explained | Race Around Condition in JK Flip-Flop | JK Flip- Flop Truth Table, Excitation table and Timing Diagram - ALL ABOUT ELECTRONICS
Clocked or Triggered Flip Flops - Positive,Negative edge triggered Flip flops
For each of the positive edge triggered J K flip flop used in the following figure, the propagation delay is ΔT.Which of the following waveforms correctly represents the output at Q1?
File:JK Flip-flop (Simple) Symbol.svg - Wikipedia
SOLVED: Consider the negative edge triggered JK flip-flop with active low preset and clear in Figure 2. Draw the output Q given the following timing diagram: CLK PRE CLA . ...... 1......1 ...V ...t...... ........... ... .. ...
digital logic - Edge triggering seems to me leaving every circuit in an inconsistent state? - Electrical Engineering Stack Exchange
JK Flip-flops
Solved] Two edge-triggered J-K flip-flops are shown in Figure 7-77. If the... | Course Hero
Flip-flop circuits
Negative edge-triggered JK Flip Flop with CLR' and PRE' input. - YouTube
